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| ( DataSheet : www..com ) MIPS32 4KpTM Processor Core Datasheet March 6, 2002 The MIPS32TM 4KpTM core from MIPS(R) Technologies is a member of the MIPS32 4KTM processor core family. It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products. The 4Kp core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications. The 4Kp core implements the MIPS32 Architecture and contains all MIPS IITM instructions; special multiply-accumulate (MAC), conditional move, prefetch, wait, and leading zero/one detect instructions; and the 32-bit privileged resource architecture. The Memory Management Unit consists of a simple, fixed Block Address Translation (BAT) mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer based MMU. Instruction and data caches are fully configurable from 0 - 16 Kbytes in size. In addition, each cache can be organized as direct-mapped or 2-way, 3-way, or 4-way set associative. Load and fetch cache misses only block until the critical word becomes available. The pipeline resumes execution while the remaining words are being written to the cache. Both caches are virtually indexed and physically tagged to allow them to be accessed in the same clock that the address is translated. An optional Enhanced JTAG (EJTAG) block allows for single-stepping of the processor as well as instruction and data virtual address breakpoints. Figure 1 shows a block diagram of the 4Kp core. The core is divided into required and optional blocks as shown. Processor Core EJTAG Mul/Div Unit Instruction Cache On-Chip Bus(es) System Coprocessor BAT Data Cache Power Mgmt. Fixed/Required Optional Figure 1 4Kp Core Block Diagram Features * 32-bit Address and Data Paths MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. www..com BIU MMU Thin I/F Execution Core Cache Control * MIPS32-Compatible Instruction Set - - - - - - - All MIPS II Instructions Multiply-Accumulate and Multiply-Subtract Instructions (MADD, MADDU, MSUB, MSUBU) Targeted Multiply Instruction (MUL) Zero/One Detect Instructions (CLZ, CLO) Wait Instruction (WAIT) Conditional Move Instructions (MOVZ, MOVN) Prefetch Instruction (PREF) Architecture Overview The 4Kp core contains both required and optional blocks. Required blocks are the lightly shaded areas of the block diagram in Figure 1 and must be implemented to remain MIPS-compliant. Optional blocks can be added to the 4Kp core based on the needs of the implementation. The required blocks are as follows: * Execution Unit * Multiply/Divide Unit (MDU) * System Control Coprocessor (CP0) * Memory Management Unit (MMU) * Block Address Translation (BAT) * Cache Controllers * Bus Interface Unit (BIU) * Power Management Optional blocks include: * Instruction Cache * Data Cache * Scratchpad RAM * Enhanced JTAG (EJTAG) Controller The section entitled "4Kp Core Required Logic Blocks" on page 3 discusses the required blocks. The section entitled "4Kp Core Optional Logic Blocks" on page 10 discusses the optional blocks. * Programmable Cache Sizes - - - - - - - - - Individually configurable instruction and data caches Sizes from 0 - 16KB Direct Mapped, 2-, 3-, or 4-Way Set Associative Loads block only until critical word is available Write-through, no write-allocate 16-byte cache line size, word sectored Virtually indexed, physically tagged Cache line locking support Non-blocking prefetches * Scratchpad RAM Support - - - Can optionally replace 1 way of the I- and/or D-cache with a fast scratchpad RAM 20 index address bits allow access of arrays up to 1MB Memory-mapped registers attached to the scratchpad port can be used as a coprocessor interface * R4000(R)-style Privileged Resource Architecture - - - Count/Compare registers for real-time timer interrupts I and D watch registers for SW breakpoints Separate interrupt exception vector * Memory Management Unit - Simple Block Address Translation (BAT) mechanism * Simple Bus Interface Unit (BIU) - - - All I/Os fully registered Separate unidirectional 32-bit address and data buses Two 16-byte collapsing write buffers Pipeline Flow The 4Kp core implements a 5-stage pipeline with performance similar to the R3000(R) pipeline. The pipeline allows the processor to achieve high frequency while minimizing device complexity, reducing both cost and power consumption. The 4Kp core pipeline consists of five stages: * Instruction (I Stage) * Execution (E Stage) * Memory (M Stage) * Align (A Stage) * Writeback (W stage) The 4Kp core implements a bypass mechanism that allows the result of an operation to be forwarded directly to the * Multiply/Divide Unit - - - 32 clock latency on multiply 34 clock latency on multiply-accumulate 33-35 clock latency on divide (sign-dependent) * Power Control - - - Minimum frequency: 0 MHz Power-down mode (triggered by WAIT instruction) Support for software-controlled clock divider * EJTAG Debug Support with single stepping, virtual instruction and data address breakpoints 2 MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. instruction that needs it without having to write the result to the register and then read it back. Figure 2 shows a timing diagram of the 4Kp core pipeline. * A multiply-accumulate operation stalls for 33 clocks in the M stage. * A divide operation stalls for 32-34 clocks in the M stage. A Stage: Align I E M Bypass Bypass A W During the Align stage: * A separate aligner aligns load data to its word boundary. I-Cache RegRd I Dec ALU Op D-AC D-Cache Align RegW I-A1 I-A2 * A multiply/divide operation updates the HI/LO registers. RegW MUL mul, div RegW * A MUL operation makes the result available for writeback. The actual register writeback is performed in the W stage. W Stage: Writeback Figure 2 4Kp Core Pipeline I Stage: Instruction Fetch During the Instruction fetch stage: * An instruction is fetched from instruction cache. E Stage: Execution * For register-to-register or load instructions, the instruction result is written back to the register file during the W stage. 4Kp Core Required Logic Blocks The 4Kp core consists of the following required logic blocks as shown in Figure 1. These logic blocks are defined in the following subsections: * Execution Unit * Multiply/Divide Unit (MDU) * System Control Coprocessor (CP0) * Memory Management Unit (MMU) * Block Address Translation (BAT) * Cache Controller * Bus Interface Control (BIU) * Power Management During the Execution stage: * Operands are fetched from register file. * The arithmetic logic unit (ALU) begins the arithmetic or logical operation for register-to-register instructions. * The ALU calculates the data virtual address for load and store instructions. * The ALU determines whether the branch condition is true and calculates the virtual branch target address for branch instructions. * Instruction logic selects an instruction address. * All multiply and divide operations begin in this stage. M Stage: Memory Fetch Execution Unit During the memory fetch stage: * The arithmetic ALU operation completes. * The data cache fetch and the data virtual-to-physical address translation are performed for load and store instructions. * Data cache look-up is performed and a hit/miss determination is made. * A multiply operation stalls for 31 clocks in the M stage. MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. The 4Kp core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The 4Kp core contains thirty-two 32-bit generalpurpose registers used for integer operations and address calculation. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. 3 The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions * Arithmetic Logic Unit (ALU) for performing bitwise logical operations * Shifter & Store Aligner Table 1 4Kp Core Integer Multiply/Divide Unit Operation Latencies Operand Sign Latency Opcode DIV pos/pos any/neg neg/pos 33 34 35 The MIPS architecture defines that the results of a multiply or divide operation be placed in the HI and LO registers. Using the move-from-HI (MFHI) and move-from-LO (MFLO) instructions, these values can be transferred to the general-purpose register file. As an enhancement to the MIPS II ISA, the 4Kp core implements an additional multiply instruction, MUL, which specifies that multiply results be placed in the primary register file instead of the HI/LO register pair. Two other instructions, multiply-add (MADD) and multiply-subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations, respectively. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. Multiply/Divide Unit (MDU) The 4Kp core contains a multiply/divide unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the integer unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows the long-running MDU operations to be partially masked by system stalls and/or other integer unit instructions. Multiply and divide operations are implemented with a simple 1 bit per clock iterative algorithm. Any attempt to issue a subsequent MDU instruction while a multiply/ divide is still active causes an MDU pipeline stall until the operation is completed. Table 1 lists the latency (number of cycles until a result is available) for the 4Kp core multiply and divide instructions. The latencies are listed in terms of pipeline clocks. Table 1 4Kp Core Integer Multiply/Divide Unit Operation Latencies Operand Sign Latency System Control Coprocessor (CP0) In the MIPS architecture, CP0 is responsible for the virtualto-physical address translation and cache protocols, the exception control system, the processor's diagnostics capability, the operating modes (kernel, user, and debug), and interrupts enabled or disabled. Configuration information such as cache size and set associativity is available by accessing the CP0 registers, listed in Table 2. Table 2 Register Number Coprocessor 0 Registers in Numerical Order Register Name Function Opcode 0 MUL, MULT, MULTU MADD, MADDU, MSUB, MSUBU DIVU any 33 any any 32 1 34 2 3 Index1 Random1 EntryLo01 EntryLo11 Reserved in the 4Kp core. Reserved in the 4Kp core. Reserved in the 4Kp core. Reserved in the 4Kp core. 4 MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Table 2 Register Number Coprocessor 0 Registers in Numerical Order Register Name Function 4 5 6 7 8 9 10 11 12 13 14 15 16 16 17 18 19 20 - 22 23 24 25 - 27 28 29 30 31 Context2 PageMask1 Wired1 Reserved BadVAddr2 Count2 EntryHi1 Compare2 Status2 Cause2 EPC2 PRId Config Config1 LLAddr WatchLo2 WatchHi2 Reserved Debug3 DEPC3 Reserved TagLo/ DataLo Reserved ErrorEPC2 DeSave3 Pointer to page table entry in memory. Reserved in the 4Kp core. Reserved in the 4Kp core. Reserved. Reports the address for the most recent address-related exception. Processor cycle count. Reserved in the 4Kp core. Timer interrupt control. Processor status and control. Cause of last general exception. Program counter at last exception. Processor identification and revision. Configuration register. Configuration register 1. Load linked address. Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including boundary cases in data, external events, or program errors. Table 3 shows the exception types in order of priority. Table 3 Exception 4Kp Core Exception Types Description Reset Soft Reset DSS DINT Assertion of SI_ColdReset signal. Assertion of SI_Reset signal. EJTAG Debug Single Step. EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the EjtagBrk bit in the ECR register. Assertion of EB_NMI signal. TLB write that conflicts with an existing entry. Assertion of unmasked hardware or software interrupt signal. Deferred Watch (unmasked by K|DM>!(K|DM) transition). EJTAG debug hardware instruction break matched. A reference to an address in one of the watch registers (fetch). Fetch address alignment error. Fetch reference to protected address. NMI Machine Check Interrupt Deferred Watch DIB WATCH Low-order watchpoint address. High-order watchpoint address. Reserved. Debug control and exception status. Program counter at last debug exception. Reserved. Low-order portion of cache tag interface. Reserved. Program counter at last error. Debug handler scratchpad register. TLBL IBE DBp Sys Bp RI CpU Ov Tr AdEL Fetch TLB miss. Instruction fetch bus error. EJTAG Breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Execution of BREAK instruction. Execution of a Reserved Instruction. Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). 1. Registers used in memory management. 2. Registers used in exception processing. 3. Registers used during debug. MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. 5 Table 3 4Kp Core Exception Types (Continued) Description 0xFFFFFFFF Exception Memory Mapped 0xFF400000 0xFF3FFFFF 0xFF200000 0xF1FFFFFF 0xE0000000 DDBL / DDBS EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address+value). A reference to an address in one of the watch registers (data). Load address alignment error. Load reference to protected address. Memory/EJTAG1 Memory Mapped kseg3 WATCH AdEL 0xDFFFFFFF Kernel virtual address space Mapped, 512 MB Kernel virtual address space Unmapped, 512 MB Uncached Kernel virtual address space Unmapped, 512 MB kseg2 0xC0000000 0xBFFFFFFF kseg1 AdES Store address alignment error. Store to protected address. 0xA0000000 0x9FFFFFFF kseg0 DBE DDBL Load or store bus error. EJTAG data hardware breakpoint matched in load data compare. 0x80000000 0x7FFFFFFF Modes of Operation The 4Kp core supports three modes of operation: user mode, kernel mode, and debug mode. User mode is most often used for applications programs. Kernel mode is typically used for handling exceptions and operating system kernel functions, including CP0 management and I/ O device accesses. An additional Debug mode is used during system bring-up and software development. Refer to the EJTAG section for more information on debug mode. User virtual address space Mapped, 2048 MB kuseg 0x00000000 1. This space is mapped to memory in user of kernel mode, and by the EJTAG module in debug mode. Figure 3 4Kp Core Virtual Address Map Memory Management Unit (MMU) The 4Kp core contains an MMU that interfaces between the execution unit and the cache controller. The 4Kp core provides a simple block address translation (BAT) mechanism that is smaller than the TLB in the MIPS32 4KcTM core and more easily synthesized. Like the TLB, the BAT performs virtual-to-physical address translation and provides attributes for the different segments. Those segments that are unmapped in the 4Kc core's TLB implementation (kseg0 and kseg1) are translated identically by the BAT. 6 MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Figure 4 shows how the BAT is implemented in the 4Kp core. Virtual Address Instruction Cache Tag RAM Comparator Instruction Hit/Miss BAT Data Hit/Miss Data Address Calculator Virtual Address Comparator Table 5 Segment Cacheability of Segments with Block Address Translation Virtual Address Range Cacheability Instruction Address Calculator kseg1 kseg2 0xA000_00000xBFFF_FFFF 0xC000_00000xDFFF_FFFF Always uncacheable Controlled by the K23 field (bits 30:28) of the Config register. See Table 4 for mapping. Controlled by the K23 field (bits 30:28) of the Config register. See Table 4 for mapping. Data Cache RAM kseg3 0xE000_00000xFFFF_FFFF Figure 4 Address Translation During a Cache Access The BAT also determines the cacheability of each segment. These attributes are controlled via bits in the Config register. Table 4 shows the encoding for the K23 (bits 30:28), KU (bits 27:25), and K0 (bits 2:0) bits of the Config register. Table 4 Cache Coherency Attributes Cache Coherency Attribute The BAT performs a simple translation to map from virtual addresses to physical addresses. This mapping is shown in Figure 5. Virtual Address kseg3 0xE000_0000 Physical Address kseg3 0xE000_0000 Config Register Fields K23, KU, and K0 kseg2 0xC000_0000 kseg2 0xC000_0000 0*, 1*, 3, 4*, 5*, 6* 2, 7* Cacheable, noncoherent, writethrough, no write-allocate Uncached kseg1 0xA000_0000 kseg0 0x8000_0000 *2 and 3 are the required MIPS32 mappings for uncached and cacheable references, other values may have different meanings in other MIPS32 processors useg/kuseg useg/kuseg 0x4000_0000 In the 4Kp core, no translation exceptions can be taken, although address errors are still possible. Table 5 Segment reserved 0x2000_0000 kseg0/kseg1 Cacheability of Segments with Block Address Translation Virtual Address Range Cacheability 0x0000_0000 0x0000_0000 Figure 5 BAT Memory Map (ERL=0) in the 4Kp Processor Core When ERL=1, useg and kuseg become unmapped and uncached. This behavior is the same as if there was a TLB. This mapping is shown in Figure 6. useg/kuseg 0x0000_00000x7FFF_FFFF Controlled by the KU field (bits 27:25) of the Config register. See Table 4 for mapping. This segment is always uncached when ERL = 1. Controlled by the K0 field (bits 2:0) of the Config register. See Table 4 for mapping. kseg0 0x8000_00000x9FFF_FFFF MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. 7 Virtual Address kseg3 0xE000_0000 kseg2 0xC000_0000 kseg1 0xA000_0000 kseg0 0x8000_0000 Physical Address kseg3 0xE000_0000 kseg2 0xC000_0000 The write buffer is organized as two 16-byte buffers. Each buffer contains data from a single 16-byte aligned block of memory. One buffer contains the data currently being transferred on the external interface, while the other buffer contains accumulating data from the core. Data from the accumulation buffer is transferred to the external interface buffer under one of these conditions: * When a store is attempted from the core to a different 16-byte block than is currently being accumulated * SYNC Instruction * Store to an invalid merge pattern reserved 0x8000_0000 useg/kuseg useg/kuseg * Any load or store to uncached memory * A load to the line being merged 0x0000_0000 kseg0/kseg1 0x0000_0000 Figure 6 BAT Memory Map (ERL=1) in the 4Kp Processor Core Note that if the data in the external interface buffer has not been written out to memory, the core is stalled until the memory write completes. After completion of the memory write, accumulated buffer data can be written to the external interface buffer. Merge Pattern Control The 4Kp core implements two 16-byte collapsing write buffers that allow byte, halfword, tri-byte, or word writes from the core to be accumulated in the buffer into a 16-byte value before bursting the data out onto the bus in word format. Note that writes to uncached areas are never merged. The 4Kp core provides two options for merge pattern control: * No merge * Full merge In No Merge mode, writes to a different word within the same line are accumulated in the buffer. Writes to the same word cause the previous word to be driven onto the bus. In Full Merge mode, all combinations of writes to the same line are collected in the buffer. Any pattern of byte enables is possible. SimpleBE Mode To aid in attaching the 4Kp core to existing busses, there is a mode that only generates "simple" byte enables. Only byte enables representing naturally aligned byte, half, and word transactions will be generated. Legal byte enable patterns are shown in Table 6. Writes with illegal byte enable patterns will be broken into two separate write MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Cache Controllers The 4Kp core instruction and data cache controllers support caches of various sizes, organizations, and setassociativity. For example, the data cache can be 2 Kbytes in size and 2-way set associative, while the instruction cache can be 8 Kbytes in size and 4-way set associative. Each cache can each be accessed in a single processor cycle. In addition, each cache has its own 32-bit data path and both caches can be accessed in the same pipeline clock cycle. Refer to the section entitled "4Kp Core Optional Logic Blocks" on page 10 for more information on instruction and data cache organization. The cache controllers also have built-in support for replacing one way of the cache with a scratchpad RAM. See the section entitled "4Kp Core Optional Logic Blocks" on page 10 for more information on scratchpad RAMs. Bus Interface (BIU) The Bus Interface Unit (BIU) controls the external interface signals. Additionally, it contains the implementation of the 32-byte collapsing write buffer. The purpose of this buffer is to store and combine write transactions before issuing them at the external interface. Since the 4Kp core caches follow a write-through cache policy, the write buffer significantly reduces the number of writes transactions on the external interface and reduces the amount of stalling in the core due to issuance of multiple writes in a short period of time. 8 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. transactions. This splitting is independent of the merge pattern control in the write buffer. The only case where a read can generate illegal byte enables is on an uncached tribyte load (LWL/LWR). These reads will be converted into a word read on the bus. Table 6 Valid SimpleBE Byte Enable Patterns EB_BE[3:0] assertion of Reset causes a soft reset exception within the 4Kp core. In debug mode, EJTAG can request that the soft reset function be masked. It is system dependent whether this functionality is supported. In normal mode, the soft reset cannot be masked. Power Management The 4Kp core offers a number of power management features, including low-power design, active power management, and power-down modes of operation. The 4Kp core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. The 4Kp core provides two mechanisms for system-level low power support: * Register-controlled power management * Instruction-controlled power management Register-Controlled Power Management 0001 0010 0100 1000 0011 1100 1111 4Kp Core Reset The 4Kp core has two types of reset input signals: Reset and ColdReset. The ColdReset signal must be asserted on either a poweron reset or a cold reset. In a typical application, a power-on reset occurs when the machine is first turned on. A cold reset (also called a hard reset) typically occurs when the machine is already on and the system is rebooted. A cold reset completely initializes the internal state machines of the 4Kp core without saving any state information. The Reset and ColdReset signals work in conjunction with one another to determine the type of reset operation (see Table 7). Table 7 Reset The RP bit in the CP0 Status register provides a software mechanism for placing the system into a low power state. The state of the RP bit is available externally via the SI_RP signal. The external agent then decides whether to place the device in low power mode, such as by reducing the system clock frequency. Three additional bits, StatusEXL, StatusERL, and DebugDM support the power management function by allowing the user to change the power state if an exception or error occurs while the 4Kp core is in a low power state. Depending on what type of exception is taken, one of these three bits will be asserted and reflected on the SI_EXL, SI_ERL, or EJ_DebugM outputs. The external agent can look at these signals and determine whether to leave the low power state to service the exception. The following 4 power-down signals are part of the system interface and change state as the corresponding bits in the CP0 registers are set or cleared: * The SI_RP signal represents the state of the RP bit (27) in the CP0 Status register. * The SI_EXL signal represents the state of the EXL bit (1) in the CP0 Status register. * The SI_ERL signal represents the state of the ERL bit (2) in the CP0 Status register. * The EJ_DebugM signal represents the state of the DM bit (30) in the CP0 Debug register. 9 4Kp Reset Types Action ColdReset 0 1 X 0 0 1 Normal Operation, no reset. Warm or Soft reset. Cold or Hard reset. The Reset signal is asserted for a warm reset. A warm reset restarts the 4Kp core and preserves more of the processors internal state than a cold reset. The Reset signal can be asserted synchronously or asynchronously during a cold reset, or synchronously to initiate a warm reset. The MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Instruction-Controlled Power Management The second mechanism for invoking power-down mode is through execution of the WAIT instruction. When the WAIT instruction is executed, the internal clock is suspended. However, the internal timer and some of the input pins (SI_Int[5:0], SI_NMI, SI_Reset, and SI_ColdReset) continue to run. Once the CPU is in instruction-controlled power management mode, any interrupt, NMI, or reset condition causes the CPU to exit this mode and resume normal operation. The 4Kp core asserts the SI_SLEEP signal, which is part of the system interface bus, whenever the WAIT instruction is executed. The assertion of SI_SLEEP indicates that the clock has stopped and the 4Kp core is waiting for an interrupt. Data Cache The data cache is an optional on-chip memory block of up to 16 Kbytes. This virtually indexed, physically tagged cache is protected. Because the data cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access. The tag holds 22 bits of physical address, 4 valid bits, a lock bit, and the fill replacement bit. In addition to instruction-cache locking, the 4Kp core also supports a data-cache locking mechanism identical to the instruction cache. Critical data segments are locked into the cache on a "per-line" basis. The locked contents can be updated on a store hit, but cannot be selected for replacement on a cache miss. The cache-locking function is always available on all data cache entries. Entries can then be marked as locked or unlocked on a per-entry basis using the CACHE instruction. 4Kp Core Optional Logic Blocks The 4Kp core consists of the following optional logic blocks as shown in the block diagram in Figure 1. Cache Memory Configuration The 4Kp core incorporates on-chip instruction and data caches that can each be accessed in a single processor cycle. Each cache has its own 32-bit data path and can be accessed in the same pipeline clock cycle. Table 8 lists the 4Kp core instruction and data cache attributes. Table 8 4Kp Core Instruction and Data Cache Attributes Parameter Instruction Data Instruction Cache The instruction cache is an optional on-chip memory block of up to 16 Kbytes. Because the instruction cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access rather than having to wait for the physical address translation. The tag holds 22 bits of physical address, 4 valid bits, a lock bit, and the fill replacement bit. The instruction cache block also contains and manages the instruction line fill buffer. Besides accumulating data to be written to the cache, instruction fetches that reference data in the line fill buffer are serviced either by a bypass of that data, or data coming from the external interface. The instruction cache control logic controls the bypass function. The 4Kp4Kp core supports instruction-cache locking. Cache locking allows critical code or data segments to be locked into the cache on a "per-line" basis, enabling the system programmer to maximize the efficiency of the system cache. The cache-locking function is always available on all instruction-cache entries. Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction. 10 Size Organization Line Size Read Unit Write Policy 0 - 16 Kbytes 1 - 4 way set associative 16 bytes 32 bits na 0 - 16 Kbytes 1 - 4 way set associative 16 bytes 32 bits write-through without writeallocate miss word per line Miss restart after transfer of Cache Locking miss word per line Cache Protocols The 4Kp core supports the following cache protocols: MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. * Uncached: Addresses in a memory area indicated as uncached are not read from the cache. Stores to such addresses are written directly to main memory, without changing cache contents. * Write-through: Loads and instruction fetches first search the cache, reading main memory only if the desired data does not reside in the cache. On data store operations, the cache is first searched to see if the target address is cache resident. If it is resident, the cache contents are updated, and main memory is also written. If the cache look-up misses, only main memory is written. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the 4Kp core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define what registers are selected and how they are used. Debug Registers Three debug registers (DEBUG, DEPC, and DESAVE) have been added to the MIPS Coprocessor 0 (CP0) register set. The DEBUG register shows the cause of the debug exception and is used for the setting up of single-step operations. The DEPC, or Debug Exception Program Counter, register holds the address on which the debug exception was taken. This is used to resume program execution after the debug operation finishes. Finally, the DESAVE, or Debug Exception Save, register enables the saving of general-purpose registers used during execution of the debug exception handler. To exit debug mode, a Debug Exception Return (DERET) instruction is executed. When this instruction is executed, the system exits debug mode, allowing normal execution of application and system code to resume. EJTAG Hardware Breakpoints There are several types of simple hardware breakpoints defined in the EJTAG specification. These stop the normal operation of the CPU and force the system into debug mode. There are two types of simple hardware breakpoints implemented in the 4Kp core: Instruction breakpoints and Data breakpoints. The 4Kp core can be configured with the following breakpoint options: * No data or instruction breakpoints * One data and two instruction breakpoints * Two data and four instruction breakpoints Instruction breaks occur on instruction fetch operations, and the break is set on the virtual address on the bus between the CPU and the instruction cache. Instruction breaks can also be made on the ASID value used by the MMU. Finally, a mask can be applied to the virtual address to set breakpoints on a range of instructions. Data breakpoints occur on load/store transactions. Breakpoints are set on virtual address and ASID values, similar to the Instruction breakpoint. Data breakpoints can be set on a load, a store, or both. Data breakpoints can also 11 Scratchpad RAM The 4Kp core also supports replacing up to one way of each cache with a scratchpad RAM. The scratchpad RAM is user-defined and can consist of a variety of devices. The main requirement is that it must be accessible with timing similar to a regular cache RAM. This means that an index will be driven one cycle, a tag will be driven the following clock, and the scratchpad must return a hit signal and the data in the second clock. The scratchpad can thus easily contain a large RAM/ROM or memory-mapped registers. The core's interface to a scratchpad RAM is slightly different than to a regular cache RAM. Additional index bits allow access to a larger array, 1MB of scratchpad RAM versus 4KB for a cache way. The core does not automatically refill the scratchpad way and will not select it for replacement on cache misses. Additionally, stores that hit in the scratchpad will not generate write-throughs to main memory. EJTAG Debug Support The 4Kp core provides for an optional Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard user mode and kernel modes of operation, the 4Kp core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. Refer to the section called "4Kp Core Signal Descriptions" on page 16 for a list of signals EJTAG interface signals. MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. be set based on the value of the load/store operation. Finally, masks can be applied to both the virtual address and the load/store value. 4Kp Core Instructions The 4Kp core instruction set complies with the MIPS32 instruction set architecture. Table 9 provides a summary of instructions implemented by the 4Kp core. Table 9 4Kp Core Instruction Set Instruction Description Function Rd = Rs + Rt Rt = Rs + Immed Rt = Rs +U Immed Rd = Rs +U Rt Rd = Rs & Rt Rt = Rs & (016 || Immed) if Rs == Rt PC += (int)offset if Rs == Rt PC += (int)offset else Ignore Next Instruction if !Rs[31] PC += (int)offset GPR[31] = PC + 8 if !Rs[31] PC += (int)offset GPR[31] = PC + 8 if !Rs[31] PC += (int)offset else Ignore Next Instruction if !Rs[31] PC += (int)offset else Ignore Next Instruction if !Rs[31] && Rs != 0 PC += (int)offset if !Rs[31] && Rs != 0 PC += (int)offset else Ignore Next Instruction if Rs[31] || Rs == 0 PC += (int)offset if Rs[31] || Rs == 0 PC += (int)offset else Ignore Next Instruction ADD ADDI ADDIU ADDU AND ANDI BEQ BEQL Integer Add Integer Add Immediate Unsigned Integer Add Immediate Unsigned Integer Add Logical AND Logical AND Immediate Branch On Equal Branch On Equal Likely BGEZ BGEZAL Branch on Greater Than or Equal To Zero Branch on Greater Than or Equal To Zero And Link Branch on Greater Than or Equal To Zero And Link Likely BGEZALL BGEZL Branch on Greater Than or Equal To Zero Likely BGTZ BGTZL Branch on Greater Than Zero Branch on Greater Than Zero Likely BLEZ BLEZL Branch on Less Than or Equal to Zero Branch on Less Than or Equal to Zero Likely 12 MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Table 9 4Kp Core Instruction Set (Continued) Instruction Description Function if Rs[31] PC += (int)offset GPR[31] = PC + 8 if Rs[31] PC += (int)offset GPR[31] = PC + 8 if Rs[31] PC += (int)offset else Ignore Next Instruction if Rs[31] PC += (int)offset else Ignore Next Instruction if Rs != Rt PC += (int)offset if Rs != Rt PC += (int)offset else Ignore Next Instruction BLTZ BLTZAL Branch on Less Than Zero Branch on Less Than Zero And Link BLTZALL Branch on Less Than Zero And Link Likely BLTZL Branch on Less Than Zero Likely BNE BNEL Branch on Not Equal Branch on Not Equal Likely BREAK CACHE COP0 CLO CLZ DERET DIV DIVU ERET Breakpoint Cache Operation Coprocessor 0 Operation Count Leading Ones Count Leading Zeroes Return from Debug Exception Divide Unsigned Divide Return from Exception Break Exception See Software User's Manual See Software User's Manual Rd = NumLeadingOnes(Rs) Rd = NumLeadingZeroes(Rs) PC = DEPC Exit Debug Mode LO = (int)Rs / (int)Rt HI = (int)Rs % (int)Rt LO = (uns)Rs / (uns)Rt HI = (uns)Rs % (uns)Rt if SR[2] PC = ErrorEPC else PC = EPC SR[1] = 0 SR[2] = 0 LL = 0 PC = PC[31:28] || offset<<2 GPR[31] = PC + 8 PC = PC[31:28] || offset<<2 Rd = PC + 8 PC = Rs PC = Rs J JAL JALR JR Unconditional Jump Jump and Link Jump and Link Register Jump Register MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. 13 Table 9 4Kp Core Instruction Set (Continued) Instruction Description Function Rt = (byte)Mem[Rs+offset] Rt = (ubyte))Mem[Rs+offset] Rt = (half)Mem[Rs+offset] Rt = (uhalf)Mem[Rs+offset] Rt = Mem[Rs+offset] LL = 1 LLAdr = Rs + offset Rt = immediate << 16 Rt = Mem[Rs+offset] LB LBU LH LHU LL Load Byte Unsigned Load Byte Load Halfword Unsigned Load Halfword Load Linked Word LUI LW LWL LWR MADD MADDU MFC0 MFHI MFLO MOVN MOVZ MSUB MSUBU MTC0 MTHI MTLO MUL Load Upper Immediate Load Word Load Word Left Load Word Right Multiply-Add Multiply-Add Unsigned Move From Coprocessor 0 Move From HI Move From LO Move Conditional on Not Zero Move Conditional on Zero Multiply-Subtract Multiply-Subtract Unsigned Move To Coprocessor 0 Move To HI Move To LO Multiply with register write See Software User's Manual See Software User's Manual HI | LO += (int)Rs * (int)Rt HI | LO += (uns)Rs * (uns)Rt Rt = CPR[0, n, sel] = Rt Rd = HI Rd = LO if Rt 0 then Rd = Rs if Rt = 0 then Rd = Rs HI | LO -= (int)Rs * (int)Rt HI | LO -= (uns)Rs * (uns)Rt CPR[0, n, SEL] = Rt HI = Rs LO = Rs HI | LO =Unpredictable Rd = ((int)Rs * (int)Rt)31..0 HI | LO = (int)Rs * (int)Rd HI | LO = (uns)Rs * (uns)Rd Rd = ~(Rs | Rt) Rd = Rs | Rt Rt = Rs | Immed MULT MULTU NOR OR ORI PREF SB 14 Integer Multiply Unsigned Multiply Logical NOR Logical OR Logical OR Immediate Prefetch Store Byte Load Specified Line into Cache (byte)Mem[Rs+offset] = Rt MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Table 9 4Kp Core Instruction Set (Continued) Instruction Description Function if LL = 1 mem[Rs+offset] = Rt Rt = LL SC Store Conditional Word SDBBP SH SLL SLLV SLT Software Debug Break Point Store Half Shift Left Logical Shift Left Logical Variable Set on Less Than Trap to SW Debug Handler (half)Mem[Rs+offset] = Rt Rd = Rt << sa Rd = Rt << Rs[4:0] if (int)Rs < (int)Rt Rd = 1 else Rd = 0 if (int)Rs < (int)Immed Rt = 1 else Rt = 0 if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0 if (uns)Rs < (uns)Immed Rd = 1 else Rd = 0 Rd = (int)Rt >> sa Rd = (int)Rt >> Rs[4:0] Rd = (uns)Rt >> sa Rd = (uns)Rt >> Rs[4:0] NOP Rt = (int)Rs - (int)Rd Rt = (uns)Rs - (uns)Rd Mem[Rs+offset] = Rt SLTI Set on Less Than Immediate SLTIU Set on Less Than Immediate Unsigned SLTU Set on Less Than Unsigned SRA SRAV SRL SRLV SSNOP SUB SUBU SW SWL SWR SYNC SYSCALL TEQ TEQI Shift Right Arithmetic Shift Right Arithmetic Variable Shift Right Logical Shift Right Logical Variable Superscalar Inhibit No Operation Integer Subtract Unsigned Subtract Store Word Store Word Left Store Word Right Synchronize System Call Trap if Equal Trap if Equal Immediate See Software User's Manual See Software User's Manual See Software User's Manual SystemCallException if Rs == Rt TrapException if Rs == (int)Immed TrapException MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. 15 Table 9 4Kp Core Instruction Set (Continued) Instruction Description Function if (int)Rs >= (int)Rt TrapException if (int)Rs >= (int)Immed TrapException if (uns)Rs >= (uns)Immed TrapException if (uns)Rs >= (uns)Rt TrapException if (int)Rs < (int)Rt TrapException if (int)Rs < (int)Immed TrapException if (uns)Rs < (uns)Immed TrapException if (uns)Rs < (uns)Rt TrapException if Rs != Rt TrapException if Rs != (int)Immed TrapException TGE TGEI TGEIU TGEU TLT TLTI TLTIU TLTU TNE TNEI WAIT XOR XORI Trap if Greater Than or Equal Trap if Greater Than or Equal Immediate Trap if Greater Than or Equal Immediate Unsigned Trap if Greater Than or Equal Unsigned Trap if Less Than Trap if Less Than Immediate Trap if Less Than Immediate Unsigned Trap if Less Than Unsigned Trap if Not Equal Trap if Not Equal Immediate Wait for Interrupts Exclusive OR Exclusive OR Immediate Stall until interrupt occurs Rd = Rs ^ Rt Rt = Rs ^ (uns)Immed 4Kp Core Signal Descriptions This section describes the signal interface of the 4Kp microprocessor core. The pin direction key for the signal descriptions is shown in Table 10 below. Table 10 4Kp Core Signal Direction Key Dir Description I O A S Input to the 4Kp core sampled on the rising edge of the appropriate CLK signal. Output of the 4Kp core, unless otherwise noted, driven at the rising edge of the appropriate CLK signal. Asynchronous inputs that are synchronized by the core. Static input to the 4Kp core. These signals are normally tied to either power or ground and should not change state while SI_ColdReset is deasserted. The 4Kp core signals are listed in Table 11 below. Note that the signals are grouped by logical function, not by expected physical location. All signals, with the exception of EJ_TRST_N, are active-high signals. EJ_DINT and 16 SI_NMI go through edge-detection logic so that only one exception is taken each time they are asserted. MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Table 11 4Kp Signal Descriptions Signal Name Type Description System Interface Clock Signals: SI_ClkIn SI_ClkOut Reset Signals: SI_ColdReset SI_NMI SI_Reset Power Management Signals: SI_ERL SI_EXL O O This signal represents the state of the ERL bit (2) in the CP0 Status register and indicates the error level. The core asserts SI_ERL whenever a Reset, Soft Reset, or NMI exception is taken. This signal represents the state of the EXL bit (1) in the CP0 Status register and indicates the exception level. The core asserts SI_EXL whenever any exception other than a Reset, Soft Reset, NMI, or Debug exception is taken. This signal represents the state of the RP bit (27) in the CP0 Status register. Software can write this bit to indicate that the device can enter a reduced power mode. This signal is asserted by the core whenever the WAIT instruction is executed. The assertion of this signal indicates that the clock has stopped and that the core is waiting for an interrupt. A A A Hard/Cold Reset Signal. Causes a Reset Exception in the core. Non-Maskable Interrupt. An edge detect is used on this signal. When this signal is sampled asserted (high) one clock after being sampled deasserted, an NMI is posted to the core. Soft/Warm Reset Signal. Causes a SoftReset Exception in the core. I O Clock Input. All inputs and outputs, except a few of the EJTAG signals, are sampled and/or asserted relative to the rising edge of this signal. Reference Clock for the External Bus Interface. This clock signal provides a reference for deskewing any clock insertion delay created by the internal clock buffering in the core. SI_RP SI_SLEEP Interrupt Signals: SI_Int[5:0] O O A Active-high Interrupt Pins. These signals are driven by external logic and, when asserted, indicate the corresponding interrupt exception to the core. These signals go through synchronization logic and can be asserted asynchronously to SI_ClkIn. This signal is asserted whenever the Count and Compare registers match and is deasserted when the Compare register is written. In order to have timer interrupts, this signal needs to be brought back into the 4K core on one of the 6 SI_Int interrupt pins. Traditionally, this has been accomplished via muxing SI_TimerInt with SI_Int[5]. Exposing SI_TimerInt as an output allows more flexibility for the system designer. Timer interrupts can be muxed or ORed into one of the interrupts, as desired in a particular system. In a complex system, it could even be fed into a priority encoder to allow SI_Int[5:0] to map up to 63 interrupt sources. SI_TimerInt O Configuration Inputs: SI_Endian S Indicates the base endianess of the core. EB_Endian Base Endian Mode 0 1 Little Endian Big Endian MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. 17 Table 11 4Kp Signal Descriptions Signal Name Type Description SI_MergeMode[1:0] S The state of these signals determines the merge mode for the 16-byte collapsing write buffer. Encoding Merge Mode 002 012 102 112 SI_SimpleBE[1:0] S No Merge Reserved Full Merge Reserved The state of these signals can constrain the core to only generate certain byte enables on ECTM interface transactions. This eases connection to some existing bus standards. SI_SimpleBE[1:0] Byte Enable Mode 002 012 102 112 External Bus Interface EB_ARdy EB_AValid EB_Instr EB_Write EB_Burst I O O O O All BEs allowed Naturally aligned bytes, halfwords, and words only Reserved Reserved Indicates whether the target is ready for a new address. The core will not complete the address phase of a new bus transaction until the clock cycle after EB_ARdy is sampled asserted. When asserted, indicates that the values on the address bus and access types lines are valid, signifying the beginning of a new bus transaction. EB_AValid must always be valid. When asserted, indicates that the transaction is an instruction fetch versus a data reference. EB_Instr is only valid when EB_AValid is asserted. When asserted, indicates that the current transaction is a write. This signal is only valid when EB_AValid is asserted. When asserted, indicates that the current transaction is part of a cache fill or a write burst. Note that there is redundant information contained in EB_Burst, EB_BFirst, EB_BLast, and EB_BLen. This is done to simplify the system design--the information can be used in whatever form is easiest. When asserted, indicates the beginning of the burst. EB_BFirst is always valid. When asserted, indicates the end of the burst. EB_BLast is always valid. Indicates the length of the burst. This signal is only valid when EB_AValid is asserted. EB_BLength<1:0> Burst Length EB_BFirst EB_BLast EB_BLen<1:0> O O O 0 1 2 3 EB_SBlock SI reserved 4 reserved reserved When sampled asserted, sub-block ordering is used. When sampled deasserted, sequential addressing is used. 18 MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Table 11 4Kp Signal Descriptions Signal Name Type Description EB_BE<3:0> O Indicates which bytes of the EB_RData or EB_WData buses are involved in the current transaction. If an EB_BE signal is asserted, the associated byte is being read or written. EB_BE lines are only valid while EB_AValid is asserted. EB_BE Signal Read Data Bits Sampled Write Data Bits Driven Valid EB_BE<0> EB_BE<1> EB_BE<2> EB_BE<3> EB_A<35:2> EB_WData<31:0> EB_RData<31:0> EB_RdVal O O I I EB_RData<7:0> EB_RData<15:8> EB_RData<23:16> EB_RData<31:24> EB_WData<7:0> EB_WData<15:8> EB_WData<23:16> EB_WData<31:24> Address lines for external bus. Only valid when EB_AValid is asserted. EB_A[35:32] are tied to 0 in this core. Output data for writes. Input Data for reads. Indicates that the target is driving read data on EB_RData lines. EB_RdVal must always be valid. EB_RdVal may never be sampled asserted until the rising edge after the corresponding EB_ARdy was sampled asserted. Indicates that the target of a write is ready. The EB_WData lines can change in the next clock cycle. EB_WDRdy will not be sampled until the rising edge where the corresponding EB_ARdy is sampled asserted. Bus error indicator for read transactions. EB_RBErr is sampled on every rising clock edge until an active sampling of EB_RdVal. EB_RBErr sampled with asserted EB_RdVal indicates a bus error during read. EB_RBErr must be deasserted in idle phases. Bus error indicator for write transactions. EB_WBErr is sampled on the rising clock edge following an active sample of EB_WDRdy. EB_WBErr must be deasserted in idle phases. Indicates that any external write buffers are empty. The external write buffers must deassert EB_EWBE in the cycle after the corresponding EB_WDRdy is asserted and keep EB_EWBE deasserted until the external write buffers are empty. When asserted, indicates that the core is waiting for external write buffers to empty. EB_WDRdy I EB_RBErr I EB_WBErr EB_EWBE I I EB_WWBE EJTAG Interface O TAP interface. These signals comprise the EJTAG Test Access Port. These signals will not be connected if the core does not implement the TAP controller. EJ_TRST_N EJ_TCK EJ_TMS EJ_TDI EJ_TDO I I I I O Active-low Test Reset Input (TRST*) for the EJTAG TAP. At power-up, the assertion of EJ_TRST_N causes the TAP controller to be reset. Test Clock Input (TCK) for the EJTAG TAP. Test Mode Select Input (TMS) for the EJTAG TAP. Test Data Input (TDI) for the EJTAG TAP. Test Data Output (TDO) for the EJTAG TAP. MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. 19 Table 11 4Kp Signal Descriptions Signal Name Type Description EJ_TDOzstate O Drive indication for the output of TDO for the EJTAG TAP at chip level: 1: The TDO output at chip level must be in Z-state 0: The TDO output at chip level must be driven to the value of EJ_TDO IEEE Standard 1149.1-1990 defines TDO as a 3-stated signal. To avoid having a 3-state core output, the 4K core outputs this signal to drive an external 3-state buffer. Debug Interrupt: EJ_DINTsup EJ_DINT S I Value of DINTsup for the Implementation register. A 1 on this signal indicates that the EJTAG probe can use the DINT signal to interrupt the processor. Debug exception request when this signal is asserted in a CPU clock period after being deasserted in the previous CPU clock period. The request is cleared when debug mode is entered. Requests when in debug mode are ignored. Debug Mode Indication: EJ_DebugM O Asserted when the core is in Debug Mode. This can be used to bring the core out of a low power mode. In systems with multiple processor cores, this signal can be used to synchronize the cores when debugging. Device ID bits: These inputs provide an identifying number visible to the EJTAG probe. If the EJTAG TAP controller is not implemented, these inputs are not connected. These inputs are always available for soft core customers. On hard cores, the core "hardener" can set these inputs to their own values. EJ_ManufID[10:0] S Value of the ManufID[10:0] field in the Device ID register. As per IEEE 1149.1-1990 section 11.2, the manufacturer identity code shall be a compressed form of JEDEC standard manufacturer's identification code in the JEDEC Publications 106, which can be found at: http://www.jedec.org/ ManufID[6:0] bits are derived from the last byte of the JEDEC code by discarding the parity bit. ManufID[10:7] bits provide a binary count of the number of bytes in the JEDEC code that contain the continuation character (0x7F). Where the number of continuations characters exceeds 15, these 4 bits contain the modulo-16 count of the number of continuation characters. EJ_PartNumber[15:0] EJ_Version[3:0] S S Value of the PartNumber[15:0] field in the Device ID register. Value of the Version[3:0] field in the Device ID register. System Implementation Dependent Outputs: These signals come from EJTAG control registers. They have no effect on the core, but can be used to give EJTAG debugging software additional control over the system. EJ_SRstE EJ_PerRst EJ_PrRst O O O Soft Reset Enable. EJTAG can deassert this signal if it wants to mask soft resets. If this signal is deasserted, none, some, or all soft reset sources are masked. Peripheral Reset. EJTAG can assert this signal to request the reset of some or all of the peripheral devices in the system. Processor Reset. EJTAG can assert this signal to request that the core be reset. This can be fed into the SI_Reset signal. Performance Monitoring Interface These signals can be used to implement performance counters, which can be used to monitor hardware/software performance. PM_DCacheHit 20 O This signal is asserted whenever there is a data cache hit. MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Table 11 4Kp Signal Descriptions Signal Name Type Description PM_DCacheMiss PM_DTLBHit PM_DTLBMiss PM_ICacheHit PM_ICacheMiss PM_InstComplete PM_ITLBHit PM_ITLBMiss PM_JTLBHit PM_JTLBMiss PM_WTBMerge PM_WTBNoMerge Scan Test Interface O O O O O O O O O O O O This signal is asserted whenever there is a data-cache miss. This signal is not used in the 4Kp processor core and is tied to ground. This signal is not used in the 4Kp processor core and is tied to ground. This signal is asserted whenever there is an instruction-cache hit. This signal is asserted whenever there is an instruction-cache miss. This signal is asserted each time an instruction completes in the pipeline. This signal is not used in the 4Kp processor core and is tied to ground. This signal is not used in the 4Kp processor core and is tied to ground. This signal is not used in the 4Kp processor core and is tied to ground. This signal is not used in the 4Kp processor core and is tied to ground. This signal is asserted whenever there is a successful merge in the write-through buffer. This signal is asserted whenever a non-merging store is written to the write-through buffer. These signals provide the interface for testing the core. The use and configuration of these pins are implementation-dependent. ScanEnable ScanMode ScanIn 4Kp Core Bus Transactions The 4Kp core implements the ECTM interface for its bus transactions. This interface uses a pipelined, in-order protocol with independent address, read data, and write data buses. The following subsections describe the four basic bus transactions: single read, single write, burst read, and burst write. and byte enable information onto EB_BE[3:0]. To maximize performance, the EC interface does not define a maximum number of outstanding bus cycles. Instead it provides the EB_ARdy input signal. This signal is driven by external logic and controls the generation of addresses on the bus. In the 4Kp core, the address is driven whenever it becomes available, regardless of the state of EB_ARdy. However, the 4Kp4Kp core always continues to drive the address until the clock after EB_ARdy is sampled asserted. For example, at the rising edge of the clock 2 in Figure 7, the EB_ARdy signal is sampled low, indicating that external logic is not ready to accept the new address. However, the 4Kp core still drives EB_A[35:2] in this clock as shown. On the 21 Single Read Figure 7 shows the basic timing relationships of signals during a simple read transaction. During a single read cycle, the 4Kp core drives the address onto EB_A[35:2] MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. rising edge of clock 3, the 4Kp core samples EB_ARdy asserted and continues to drive the address until the rising edge of clock 4. Clock # 1 2 3 4 5 6 7 8 Clock # 1 2 3 4 5 6 7 8 EB_Clk Address and Control held until clock after EB_ARdy sampled asserted EB_ARdy EB_A[35:2] Addr Wait Valid EB_Clk Address and Control held until clock after EB_ARdy sampled asserted Addr Wait Valid EB_ARdy EB_A[35:2] EB_Instr, EB_BE[3:0], EB_AValid EB_RData[31:0] EB_RdVal EB_RBErr EB_Write EB_BE[3:0] Valid Valid EB_AValid Data is Driven until clock after EB_WDRdy Driven by system logic EB_WData[31:0] Valid Driven by system logic Valid EB_WDRdy EB_WBErr Figure 8 Single Write Transaction Timing Diagram EB_Write Figure 7 Single Read Transaction Timing Diagram The EB_Instr signal is only asserted during a single read cycle if there is an instruction fetch from non-cacheable memory space. The EB_AValid signal is driven in each clock that EB_A[35:2] is valid on the bus. The 4Kp core drives EB_Write low to indicate a read transaction. The EB_RData[31:0] and EB_RdVal signals are first sampled on the rising edge of clock 4, one clock after EB_ARdy is sampled asserted. Data is sampled on every clock thereafter until EB_RdVal is sampled asserted. If a bus error occurs during the data transaction, external logic asserts EB_RBErr in the same clock as EB_RdVal. Burst Read The 4Kp core is capable of generating burst transactions on the bus. A burst transaction is used to transfer multiple data items in one transaction. Clock # EB_Clk Addr Wait Adr1 Adr2 Adr3 1 2 3 4 5 6 7 8 EB_ARdy EB_A[35:2] Adr4 EB_Instr EB_BE[3:0] EB_Burst EB_BFirst EB_BLast Valid Single Write Figure 8 shows a typical write transaction. The 4Kp core drives address and control information onto the EB_A[35:2] and EB_BE[3:0] signals on the rising edge of clock 2. As in the single read cycle, these signals remain active until the clock edge after the EB_ARdy signal is sampled asserted. The 4Kp core asserts the EB_Write signal to indicate that a valid write cycle is on the bus and EB_AValid to indicate that valid address is on the bus. The 4Kp core drives write data onto EB_WData[31:0] in the same clock as the address and continues to drive data until the clock edge after the EB_WDRdy signal is sampled asserted. If a bus error occurs during a write operation, external logic asserts the EB_WBErr signal one clock after asserting EB_WDRdy. 22 Driven by system logic EB_AValid EB_RData[31:0] EB_RdVal EB_RBErr Read Wait Data1 Data2 Read Wait Data3 Data4 EB_Write Figure 9 Burst Read Transaction Timing Diagram Figure 9 shows an example of a burst read transaction. Burst read transactions initiated by the 4Kp core always MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. contain four data transfers in a sequence determined by the critical word (the address that caused the miss) and EB_SBlock. In addition, the data requested is always a 16byte aligned block. The order of words within this 16-byte block varies depending on which of the words in the block is being requested by the execution unit and the ordering protocol selected. The burst always starts with the word requested by the execution unit and proceeds in either an ascending or descending address order, wrapping when the block boundary is reached. Table 12 and Table 13 show the sequence of address bits 2 and 3. Table 12 Sequential Ordering Protocols Starting Address EB_A[3:2] Address Progression of EB_A[3:2] logic asserts EB_RdVal to indicate that valid data is on the bus. The 4Kp core latches data internally whenever EB_RVal is sampled asserted. Note that on the rising edge of clocks 3 and 6 in Figure 9, the EB_RdVal signal is sampled deasserted, causing wait states in the data return. There is also an address wait state caused by EB_ARdy being sampled deasserted on the rising edge of clock 4. Note that the core holds address 3 on the EB_A bus for an extra clock because of this wait state. External logic asserts the EB_RBErr signal in the same clock as data if a bus error occurs during that data transfer. Burst Write Burst write transactions are used to empty one of the write buffers. A burst write transaction is only performed if the write buffer contains 16 bytes of data associated with the same aligned memory block, otherwise individual write transactions are performed. Figure 10 shows a timing diagram of a burst write transaction. Unlike the read burst, a write burst always begins with EB_A[3:2] equal to 00b. Clock # 1 2 3 4 5 6 7 8 00 01 10 11 00, 01, 10, 11 01, 10, 11, 00 10, 11, 00, 01 11, 00, 01, 10 Table 13 Sub-Block Ordering Protocols Starting Address EB_A[3:2] Address Progression of EB_A[3:2] EB_Clk EB_ARdy EB_A[35:2] Adr1 Adr2 Adr3 Adr4 00 01 10 11 00, 01, 10, 11 EB_BE[3:0] 01, 00, 11, 10 EB_Write 10, 11, 00, 01 EB_Burst 11, 10, 01, 00 EB_BFirst Driven by system logic The 4Kp4Kp core drives address and control information onto the EB_A[35:2] and EB_BE[3:0] signals on the rising edge of clock 2. As in the single read cycle, these signals remain active until the clock edge after the EB_ARdy signal is sampled asserted. The 4Kp core continues to drive EB_AValid as long as a valid address is on the bus. The EB_Instr signal is asserted if the burst read is for an instruction fetch. The EB_Burst signal is asserted while the address is on the bus to indicate that the current address is part of a burst transaction. The 4Kp core asserts the EB_BFirst signal in the same clock as the first address is driven and the EB_BLast signal in the same clock as the last address to indicate the start and end of a burst cycle. The 4Kp core first samples the EB_RData[31:0] signals two clocks after EB_ARDy is sampled asserted. External MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 EB_BLast EB_AValid EB_WData[31:0] Write Wait Data2 Data3 Data4 Data1 EB_WDRdy EB_WBErr Write Wait Figure 10 Burst Write Transaction Timing Diagram The 4Kp core drives address and control information onto the EB_A[35:2] and EB_BE[3:0] signals on the rising edge of clock 2. As in the single read cycle, these signals remain active until the clock edge after the EB_ARdy signal is sampled asserted. The 4Kp core continues to drive EB_AValid as long as a valid address is on the bus. 23 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. The 4Kp core asserts the EB_Write, EB_Burst, and EB_AValid signals during the time the address is driven. EB_Write indicates that a write operation is in progress. The assertion of EB_Burst indicates that the current operation is a burst. EB_AValid indicates that valid address is on the bus. The 4Kp core asserts the EB_BFirst signal in the same clock as address 1 is driven to indicate the start of a burst cycle. In the clock that the last address is driven, the 4Kp core asserts EB_BLast to indicate the end of the burst transaction. In Figure 10, the first data word (Data1) is driven in clocks 2 and 3 due to the EB_WDRdy signal being sampled deasserted at the rising edge of clock 2, causing a wait state. When EB_WDRdy is sampled asserted on the rising edge of clock 3, the 4Kp core responds by driving the second word (Data2). External logic drives the EB_WBErr signal one clock after the corresponding assertion of EB_WDRdy if a bus error has occurred as shown by the arrows in Figure 10. 24 MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. Copyright (c) 1999-2002 MIPS Technologies, Inc. All rights reserved. Unpublished rights reserved under the Copyright Laws of the United States of America. This document contains information that is proprietary to MIPS Technologies, Inc. ("MIPS Technologies"). Any copying, reproducing, modifying, or use of this information (in whole or in part) which is not expressly permitted in writing by MIPS Technologies or a contractually-authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyright laws. Violations thereof may result in criminal penalties and fines. MIPS Technologies or any contractually-authorized third party reserves the right to change the information contained in this document to improve function, design or otherwise. MIPS Technologies does not assume any liability arising out of the application or use of this information, or of any error of omission in such information. Any warranties, whether express, statutory, implied or otherwise, including but not limited to the implied warranties of merchantability or fitness for a particular purpose, are excluded. Any license under patent rights or any other intellectual property rights owned by MIPS Technologies or third parties shall be conveyed by MIPS Technologies or any contractually-authorized third party in a separate license agreement between the parties. The information contained in this document shall not be exported or transferred for the purpose of reexporting in violation of any U.S. or non-U.S. regulation, treaty, Executive Order, law, statute, amendment or supplement thereto. The information contained in this document constitutes one or more of the following: commercial computer software, commercial computer software documentation or other commercial items. If the user of this information, or any related documentation of any kind, including related technical data or manuals, is an agency, department, or other entity of the United States government ("Government"), the use, duplication, reproduction, release, modification, disclosure, or transfer of this information, or any related documentation of any kind, is restricted in accordance with Federal Acquisition Regulation 12.212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies. The use of this information by the Government is further restricted in accordance with the terms of the license agreement(s) and/or applicable contract terms and conditions covering this information from MIPS Technologies or any contractually-authorized third party. MIPS(R), R3000(R), R4000(R), R5000(R) and R10000(R) are among the registered trademarks of MIPS Technologies, Inc. in the United States and certain other countries, and MIPS16TM, MIPS16eTM,MIPS32TM, MIPS64TM, MIPS-3DTM, MIPS-basedTM, MIPS ITM, MIPS IITM, MIPS IIITM, MIPS IVTM, MIPS VTM, MDMXTM, SmartMIPSTM, 4KTM, 4KcTM, 4KmTM, 4KpTM, 4KETM, 4KEcTM, 4KEmTM, 4KEpTM, 4KSTM, 4KScTM, 5KTM, 5KcTM, 5KfTM, 20KTM, 20KcTM, R20KTM, R4300TM, ATLASTM, CoreLVTM, ECTM, JALGOTM, MALTATM, MGBTM, SEADTM, SEAD-2TM, SOC-itTM and YAMONTM are among the trademarks of MIPS Technologies, Inc. All other trademarks referred to herein are the property of their respective owners. Document Number: MD00041 01.03-2B 25 MIPS32 4KpTM Processor Core Datasheet, Revision 01.07 Copyright (c) 1999-2002 MIPS Technologies Inc. All right reserved. |
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